VHDL n-input AND gate

VHDL n-input AND gate.

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-----  AND n-input -----
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LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY andn IS
GENERIC (n : INTEGER := 4);
PORT (x : IN STD_LOGIC_VECTOR(1 TO n);
f : OUT STD_LOGIC);
END andn;

ARCHITECTURE dataflow OF andn IS
SIGNAL tmp : STD_LOGIC_VECTOR(1 TO n);
BEGIN
tmp <= (OTHERS => '1');
f <= '1' WHEN x = tmp ELSE '0';
END dataflow;

You may also want to see VHDL n-input OR gate or VHDL D-Flip Flop.