VHDL n-input OR gate

VHDL n-input OR gate.

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--- OR gate n-input ---
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LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY orn IS
GENERIC (n : INTEGER := 4);
PORT (x : IN STD_LOGIC_VECTOR(1 TO n);
f : OUT STD_LOGIC);
END orn;

ARCHITECTURE dataflow OF orn IS
SIGNAL tmp : STD_LOGIC_VECTOR(1 TO n);
BEGIN
tmp <= (OTHERS => '0');
f <= '0' WHEN x = tmp ELSE '1';
END dataflow;

You may also want to see VHDL n-input AND gate or VHDL D-Flip Flop.