4/3/08

VHDL D-Flip Flop

VHDL D-Flip Flop.
For more about Flip Flops read the article from wikipedia.

---------------------
---- D Flip Flop ----
---------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;

Entity Dflipflop IS
Port(resetn,D,clock :in std_logic;
Q1,Q2 : out std_logic);
End Dflipflop;

ARCHITECTURE behavior OF Dflipflop IS
BEGIN
p1: PROCESS (resetn,D,Clock)
BEGIN
IF resetn = '0' then
Q1<='0';
Q2<='1';
ELSIF Clock'EVENT AND Clock = '1' THEN
Q1 <= D;
Q2 <= NOT D;
END IF;

END PROCESS p1;
END behavior;

You may also want to see VHDL n-input AND gate or VHDL n-input OR gate.
Del.icio.us

No comments:

Related Posts Plugin for WordPress, Blogger...