VHDL Counter

This is a VHDL counter which uses VHDL n-input AND gate , VHDL n-input OR gate and VHDL D-Flip Flop.
Counter has the following stages: 0, 1, 2, 6, 7, 10, 12, 13, 14, 15 and 0 again.
Stages 3, 4, 5, 8, 9, 11 are not used. Counter has auto correction, which mean if the circuit go to an invalid stage after some clock ticks will go back to a valid stage. Below are the VHDL structural description and instructions how to simulate using macro .do.

------------------
---- Counter  ----
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LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY counter1 IS
port(clk,reset: in std_logic;
result : out std_logic_vector(1 to 4));
End counter1;

Architecture structural of counter1 IS
COMPONENT  Dflipflop
 port(resetn,D,Clock : in std_logic;
 Q1,Q2 : out std_logic);
End Component;

COMPONENT andn
generic( N:integer:=4);
PORT (x : IN STD_LOGIC_VECTOR(1 TO N);
f : OUT STD_LOGIC);
end component;

component orn
generic( N:integer:=4);
port (x : std_logic_vector(1 to N);
f : out std_logic);
end component;

Signal da1,da2,inputa,db1,db2,inputb,dc1,dc2,
inputc,dd1,dd2,inputd:std_logic;
Signal x1,x2,x5,x6,x7,x8,x9,x12,
x13,x14 : std_logic_vector(1 to 2);
Signal x3,x4,x10,x11 : std_logic_vector(1 to 3);
SIGNAL N : std_logic_vector(1 to 10);
Begin


x1<=da1&dc2;
x2<=da1&dd2;
x3<=da2&dc1&dd1;
x4<=N(1)&N(2)&N(3);
G4: andn generic map(2) port map(x1,N(1));
G5: andn generic map(2) port map(x2,N(2));
G6: andn generic map(3) port map(x3,N(3));
G7: orn generic map(3) port map(x4,inputa);

x5<=da1&dc2;
x6<=dc1&dd2;
x7<=N(4)&N(5);
G8: andn generic map(2) port map(x5,N(4));
G9: andn generic map(2) port map(x6,N(5));
G10: orn generic map(2) port map(x7,inputb);

x8<=dc2&dd1;
x9<=da2&dc1;
x10<=db1&dc1&dd2;
x11<=N(6)&N(7)&N(8);
G11: andn generic map(2) port map(x8,N(6));
G12: andn generic map(2) port map(x9,N(7));
G13: andn generic map(3) port map(x10,N(8));
G14: orn generic map(3) port map(x11,inputc);

x12<=dc2&dd2;
x13<=db1&dd2;
x14<=N(9)&N(10);
G15: andn generic map(2) port map(x12,N(9));
G16: andn generic map(2) port map(x13,N(10));
G17: orn generic map(2) port map(x14,inputd);

G0: dflipflop port map(reset,inputa,clk,da1,da2);
G1: dflipflop port map(reset,inputb,clk,db1,db2);
G2: dflipflop port map(reset,inputc,clk,dc1, dc2);
G3: dflipflop port map(reset,inputd,clk,dd1,dd2);

result(1)<=inputa;
result(2)<=inputb;
result(3)<=inputc;
result(4)<=inputd;
End structural;

Let's consider the code above is saved in a file named counter1.vhd
Now open a new text file and write:

vlib work
vmap work work
vcom counter1.vhd
vsim counter1
force clk 0 0, 1 10 -repeat 20
force reset 1 0
add wave /counter1/*
run 250

and save it as counter.do
Now load ModelSim and write in the console:

do counter.do

You should see something like that (click to enlarge):